Digital counter circuits are well known in the prior art and have numerous applications. Such circuits take various forms. One form is the so-called synchronous counter such as is illustrated in FIG. 1 herein. The limiting factor in the speed of such a counter is the propagation delay through the flip-flop used therein. The time required for the output of the flip-flop to change states after the leading edge of a clock pulse is constant regardless of frequency. Hence the counter cannot function at frequencies above the point where a second pulse to be counted is received prior to the time when the output state from the flip-flop has changed in response to a previous pulse.
As it is always desired to increase the operating speed of electronic circuits, various approaches have been tried to increase the speed of digital counters. One approach frequently employed is to implement a previously used circuit design in a logic family which has a higher operating speed than the circuit previously used. This approach to obtaining higher speed usually comes at increased cost as the faster circuit family usually costs more than the slower circuit family.
While switching to a higher speed circuit family may produce a higher speed counter, it is a principal objective of the present invention to provide a counter which, for a given circuit family, operates at a speed which is higher than the counting speed of prior known circuits using the same circuit family.
It is a further objective of the present invention to provide a counter which is comprised of elements generally available in various circuit families and which is configured to provide a counting speed which is higher than other known counters using the same circuit family of elements.